The present invention relates to a substrate polishing apparatus for polishing a substrate such as a semiconductor wafer for planarization.
In recent years, with increasingly miniaturized semiconductor devices, more complicated device structures, and an increase in the number of multi-layer wiring layers of logic systems, semiconductor devices tend to include increasingly more ruggedness and increasingly larger steps. This is because the manufacturing of semiconductor devices involves multiple repetitions of steps for forming a thin film, micro-machining the thin film for patterning and forming aperture therethrough, and forming a next thin film.
Increased ruggedness on the surface of a semiconductor device tends to cause a failure in producing acceptable products and a reduction in yield rate due to a smaller thickness of a thin film at steps during a thin film formation, open circuits due to disconnected wires, and short-circuiting due to defective insulation between wiring layers. Also, even if such products normally operate in an initial stage, they will experience a problem of reliability for long-term use. Further, in an exposure in a lithography step, the ruggedness on an irradiated surface would cause a lens in an exposure system to partially defocus, thus making more difficult the formation of miniature patterns themselves as ruggedness are increased on the surface of the semiconductor device.
Thus, in the semiconductor device manufacturing process, increasingly more importance is being placed on the planarization techniques for planarizing the surface of a semiconductor device. Among the planarization techniques, chemical mechanical polishing (CMP) is regarded as the most important technique. The chemical mechanical polishing employs a polishing apparatus to polish a substrate such as a semiconductor wafer brought into sliding contact with a polishing surface of a polishing pad or the like while supplying a polishing liquid including grinding grains made of silica (SiO2) or the like on the polishing surface.
This type of polishing apparatus comprises a polishing table having a polishing surface including a polishing pad; and a substrate holder, referred to as a “top ring,” a “carrier head” or the like for holding a semiconductor wafer. For polishing a semiconductor wafer using such a polishing apparatus, the semiconductor wafer is held by the substrate holder, while the semiconductor wafer is pressed onto the polishing table with a predetermined pressure. In this event, the polishing table and substrate holder are moved relative to each other to bring the semiconductor wafer into sliding contact with the polishing surface, thus polishing the surface of the semiconductor wafer into a flat and mirror-like surface.
In the polishing apparatus described above, when a polishing rate is constant, a polishing amount is proportional to a polishing time (processing time). Thus, the following method has conventionally been employed for determining a polishing time. Specifically, the thickness of one semiconductor substrate is measured before polishing. Then, the one semiconductor substrate is polished by a polishing apparatus for a predetermined constant time, and the thickness of the polished substrate is measured. The polishing rate is calculated from the relationship between the thickness and a required polishing time to determine an appropriate polishing time from a relationship between the polishing rate and a target thickness. Then, subsequent semiconductor substrates are polished for the calculated polishing time (see, for example, Japanese Patent No. 3311864, and Laid-open Japanese Patent Application No. 10-106984).
However, when the polishing rate thus calculated is simply applied as the basis for calculating a polishing rate for a substrate to be polished next, the polishing rate varies. If the polishing rate is limited only to one substrate, the thicknesses of substrates to be subsequently processed will largely deviate from a target value. To address this problem, a proposal has been made to save polished amounts and polishing times of semiconductor substrates which have already undergone the polishing, calculate an average polishing rate from these data, and polish a next substrate based on the average polishing rate (see, for example, Japanese Patent Publication No. 7-100297). This approach of calculating an average polishing rate based on past data provides the advantage of eliminating efforts of measuring the polishing rate from one lot to another and reducing variations in measurements.
However, when a polishing method (for example, see Laid-open Japanese Patent Application No. 8-22970) for improving the capability of eliminating ruggedness is employed for accommodating further miniaturization of semiconductor devices, the polishing rate used in a former polishing process largely differs from that used in a latter polishing process, resulting in a reduction by half of the meaning of the average polishing rate calculated in the aforementioned manner. Specifically, when the polished result shows excessive polishing or insufficient polishing, the processing time should be corrected in consideration of the polishing time at the tail end of polishing, and the use of the average polishing rate makes it difficult to calculate an optimal polishing time.
When the polished result shows insufficient polishing, additional polishing (i.e., rework) is involved, leading to an increased manufacturing cost. In addition, a polishing time in the additional polishing is set based on the experience of an operator. On the other hand, when the polished result shows excessive polishing, Cu layers within grooves for wiring will be polished away together with insulating films to cause an increased circuit resistance, in which case the overall semiconductor substrate must be discarded, resulting in a lower yield rate and a huge loss.
In some conventional substrate polishing apparatus, STI (shallow trench isolation) CMP is performed for forming device isolation by shallow trench isolation. In the STI CMP, after completely removing an SiO2 film deposited on the uppermost layer of a substrate, an underlying SiN layer is polished by a predetermined thickness before the polishing is finished. In this event, a method of sensing that the overlying SiO2 layer has been removed, known in the art, involves measuring a current of a motor for driving a top ring or a turn table, and utilizing a change in the current when a torque changes due to a transition of materials from SiO2 to SiN. However, this method implies a problem in that the operator's experience must be relied on to determine an over-polishing time for polishing a predetermined amount of SiN after detecting an exposed SiN layer.